ics343 mds 343 f 1 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com field programmable triple output ss versaclock synthesizer description the ics343 is a low cost, triple-output, field program- mable clock synthesizer. the ics343 can generate three output frequencies from 250 khz to 200 mhz, using up to three independently configurable plls. the outputs may employ spread spectrum techniques to reduce system electro-ma gnetic interference (emi). using ics? versaclock? software to configure the pll and output, the ics343 contains a one-time program- mable (otp) rom to allow field programmability. using phase-locked loop (pll) techniques, the device runs from a standard fundamental mode, inexpensive crys- tal, or clock. it can replace multiple crystals and oscilla- tors, saving board space and cost. the device also has a power down feature that tri-states the clock outputs and turns off the plls when the pdts pin is taken low. the ics343 is also available in factory-programmed custom versions for high-volume applications. features ? 8-pin soic package ? highly accurate frequency generation ? m/n multiplier pll: m = 1...2048, n = 1...1024 ? output clock frequencies up to 200 mhz ? spread spectrum capabilit y for lower system emi ? center or down spread up to 4% total ? selectable 32 khz or 120 khz modulation ? input crystal frequency from 5 to 27 mhz ? input clock frequency from 2 to 50 mhz ? operating voltage of 3.3 v, using advanced, low power cmos process ? for one output clock, use the ics341. for two output clocks, see the ics342. for more than three outputs, see the ics345 or ics348. ? available in pb (lead) free packaging block diagram crystal oscillator pdts (both outputs and pll) otp rom with pll divider values vdd gnd clk1 clk3 clk2 pll clock synthesis, spred spectrum and control circuitry x2 crystal or clock input external capacitors are required with a crystal input. x1/iclk
field programmable triple output ss versaclock mds 343 f 2 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 pin assignment 8-pin (150 mil) soic output clock selection table pin descriptions external components series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitor as with any high-performance mixed-signal ic, the ics343 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between vdd and the pcb ground plane. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) been the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each cryst al capacitor would be 20 pf [(16-6) x 2] = 20. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between x1/iclk vdd gnd pdts clk1 clk2 clk3 x2 1 2 3 4 8 7 6 5 clk2 clk2 clk3 output frequency user configurable user configurable user configurable spread amount user configurable user configurable user configurable pin number pin name pin type pin description 1 x1/iclk xi connect this pin to a crystal or external clock input. 2 vdd power connect to +3.3 v. 3 gnd power connect to ground. 4 clk1 output clock output. weak internal pull-down when tri-state. 5 clk3 output clock output. weak internal pull-down when tri-state. 6 clk2 output clock output. weak internal pull-down when tri-state. 7pdts input powers down entire chip. tri-states clk outputs when low. internal pull-up. 8 x2 xo connect this pin to a crystal, or float for clock input.
field programmable triple output ss versaclock mds 343 f 3 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 the decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi, the 33 ? series termination resistor (if needed) should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics343. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. ics343 configuration capabilities the architecture of the ics343 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. the frequency multiplier pll provides a high degree of precision. the m/n values (t he multiplier/divide values available to generate the target vco frequency) can be set within the range of m = 1 to 2048 and n = 1 to 1024. the ics343 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same pll. each output frequency can be represented as: ics versaclock software ics applies years of pll optimization experience into a user-friendly software that accepts the user?s target reference clock and output frequencies and generates the lowest jitter, lowest powe r configuration, with only a press of a button. the user does not need to have prior pll experience or determine the optimal vco frequency to support multiple output frequencies. versaclock software quickly evaluates accessible vco frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. the user may evaluate output accuracy, performance trade-off scenarios in seconds. spread spectrum modulation the ics343 utilizes frequen cy modulation (fm) to distribute energy over a range of frequencies. by modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system?s electro-magnetic interference (emi). the modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. spread spectrum modulation can be applied as either ?center spread? or ?down spread?. during center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. the effective average frequency is equal to the target frequency. in applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. in this case, the maximum frequency, including modulation, is the target frequency. the effective average frequency is less than the target frequency. the ics343 operates in both center spread and down spread modes. for center spread, the frequency can be modulated between +/- 0.125% to +/-2.0%. for down spread, the frequency can be modulated between -0.25% to -4.0%. both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common vco frequency can be identified. spread spectrum modulation rate the spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. for applications requiring the driving of ?down-circuit? plls, zero delay buffers, or those adhering to pci standards, the spread spectrum modulation rate should be set to 30-33 khz. for other applications, a 120 khz modulation option is available. outputfreq reffreq outputdivide -------------------------------------- m n ---- - ? =
field programmable triple output ss versaclock mds 343 f 4 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics343. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operat ion conditions dc electrical characteristics unless stated otherwise, vdd = 3.3v 5% , ambient temperature -40 to +85 c parameter condition min. typ. max. units supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+ 0.5 v clock outputs referenced to gnd -0.5 vdd+ 0.5 v storage temperature -65 150 c soldering temperature max 10 seconds 260 c junction temperature 125 c parameter min. typ. max. units ambient operating temperature (ics343m) 0 +70 c ambient operating temperature (ics343mi) -40 +85 c power supply voltage (measured in respect to gnd) +3.15 +3.3 +3.45 v power supply ramp time 4 ms parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.3 3.45 v operating supply current input high voltage idd configuration dependent - see versaclock tm estimates ma three 33.3333 mhz outputs, pdts = 1, no load note 1 14 ma pdts = 0 20 a input high voltage, pdts v ih vdd-0.5 v input low voltage, pdts v il 0.4 v input high voltage v ih iclk vdd/2+1 v input low voltage v il iclk vdd/2-1 v
field programmable triple output ss versaclock mds 343 f 5 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 note 1: example with 25 mhz crystal input with three outputs of 33.3 mhz, no load, and vdd = 3.3 v. ac electrical characteristics unless stated otherwise, vdd = 3.3v 5% , ambient temperature -40 to +85 c note 1: measured with 15 pf load. note 2: duty cycle is configuration dependent. most configurations are minimum 45% and maximum 55%. note 3: ics test mode output occurs for first 170 clock cycles on clk3 for each pll powered up. output high voltage (cmos high) v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v short circuit current i os 70 ma nominal output impedance z o 20 ? internal pull-up resistor r pup pdts pin 250 k ? internal pull-down resistor r pd clk output 525 k ? input capacitance c in inputs 4 pf parameter symbol conditions min. typ. max. units input frequency f in fundamental crystal 5 27 mhz input clock 2 50 mhz output frequency 0.25 200 mhz output rise time t or 20% to 80%, note 1 1 ns output fall time t of 80% to 20%, note 1 1 ns duty cycle note 2 40 49-51 60 % power-up time pll lock time from power-up, note 3 410ms pdts goes high until stable clk output, spread spectrum off, note 3 0.2 2 ms pdts goes high until stable clk output, spread spectrum on, note 3 47ms one sigma clock period jitter configuration dependent 50 ps maximum absolute jitter t ja deviation from mean. configuration dependent + 200 ps parameter symbol conditions min. typ. max. units
field programmable triple output ss versaclock mds 343 f 6 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 thermal characteristics parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
field programmable triple output ss versaclock mds 343 f 7 revision 090704 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics343 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information ?lf? denotes pb (lead) free package. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking (for both) shipping packaging package temperature ics343mp 343mp (top line) tubes 8-pin soic 0 to +70 c ICS343MIP 343mip (top line) tubes 8-pin soic -40 to +85 c ics343mlf 343mlf (top line) tubes 8-pin soic 0 to +70 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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